0.8 High-speed Pipelined Architecture Of The Mcu Design

With the development of semiconductor technology and VLSI(Very large ScaleI ntegration), the disadvantage of the traditional MCU was exposed because of its defect. Its speed, scale and performance can't meet the more and more requirements from the users. Thetechnology of System on a Chip (SoC) is widely used in embedded system now for its advantage.MCS-8051 is a classic 8-bit MCU that is still applied in many fields today, but it has low instruction execution efficiency that limit the application in high-speed system. The pipeline design method is known to have the high performance in speed. In this dissertation, we propose a synchronous processor is compatible with 8051.The research of this dissertation is focused on how to design a high-speed MCU based on pipeline structure. The main content is such aspect:1) According to the theory of pipeline, we analyzed the instruction set of 8051 and proposed a 3-stage synchronous pineline architecture as follow: instruction fetch(IF) , instruction decode (ID) and execution(EX).2) We divided the MCU structure into three modules according to the three stages pipeline. We will introduce architecture of each module respectively. Hardware logic is adopted for instruction decoding. The process of instruction execution is actually the course of data flow through data path. We discussed how to establish of data path and depicted the data flow of main instructions in detail.3) We develop the functions towards system modules, for example: JTAG module and DAC serial controller module. The functions satisfy the demands of multicores debug and data convert.4) We used top-down design method .The MCU is described with verilog in RTL level. The results of simulation and synthesis proved the correctness of the design. We analyzed the synthesis results and implement the MCU with FPGA finally.The MCU design is 7 times faster than MCS-8051 through the verification on software and FPGA.