Conversion Circuit Design, Based On The Number Of Time Of Pld

Wantanabe realized an all digital ADC design based on his TDC design^[3] . An ASIC chip wasmanufactured on a 0.45 mm ² chip in 0.8um CMOS line.Unfortunately, the ATC way used by Wantanabe in paper^[1] uses the principle which points out that the delay time for a CMOS gate is proportional to the voltage applied on it. It is not possible for PLD realization based on the principle. We all know that ASIC realization has many disadvantages such as high design effort and cost, high manufacturing risk, and hard design re-use etc. As the development of high resolution digital TDC, the PLD realization of digit TDC becomes possible.This paper focuses on the PLD realization of digit TDC. The realization of Wantanabe's way for TDC design is introduced. And lots of problems have to be solved to realize the design. Test results are given in this paper based on EPM7128SLC84-15 CPLD chip belonging to MAX7000S series^[17] and the resolution is 4.26ns with nonlinearity less than±1/10LSB.It seems difficult to realize Wantanabe's way on FPGA chips. This paper proposes an improving way which can work properly. The simulations are done on QuartusII Web Edition 4.2^[33], and the realization on FPGA chip belonging to Cyclone series^[19] is described. Test results are given as well.A digital ADC could be integrated by two circuit part, ATC and TDC. Paper^[37] proposed a method based on mono stable circuit. Obviously, the TDC plays an important role in such designs.All designs in this paper are fulfilled using hardware description language.