Turbo Coding-decoding Technology And Dsp Implementation

Noises and distortions are involved in digital communication system inevitably, so error control coding must be included in the system. Shannon published his paper "A mathematical theory of communication" in 1948, which accelerated the development of error coding greatly. Turbo code was first discovered in 1993. Because of its near Shannon limit performance, turbo code has been the focus of channel coding area quickly. Many researchers have done large studies about turbo code. Along with the development of fundamental theory, turbo code is coming into application area. Because of high complexity of algorithm, long time delay and large store space about the turbo decoder, it's one of important researches about turbo code to design simple and effective decoding algorithm to get excellent performance decoder.In this paper, in order to implement the turbo decoder on DSP, the iterative decoding algorithm and some technical problems in decoder implementation are thoroughly researched. Based on the analysis of decoding algorithm, the turbo decoder strcuture is simplified and the complexity of algorithm and the storage of memory needed are reduced, leading to the realization on DSP. The following parts are included in this thesis.Firstly, the strcutures of encoder and decoder are introduced and the iterative process of decoder as well. The interleaver is analyzed, especially the interleave algorithm of 3GPP.Secondly, the principle of MAP algorithm and MAX-Log-MAP algorithm, the deducing and the step for calculation of algorithm are discussed. The branch metrics and backward metrics have been simplified in the MAX-Log-MAP algorithm. Based on analysis of iterative decoding procedure, the decoding process without estimation of SNR is proposed. The performance of different iterative number in turbo decoder is discussed through matlab simulation.Thirdly, in order to implement the turbo decoder, some important problem are considered, such as fix-point quantification of received data, over-flow of calculation of backward and forward and RAM space needed. A new way to avoid over-flow of calculation is proposed, only to calculate the difference of the forward and backward metrics and the value range of difference metrics is very small. It can avoid over-flow of calculation effectively. Parallel calculation, which is forward metric and log-likelihood ratios (LLR) are calculated synchronously after backward metric is computed, is adopted in the iterative decoding process. This method reduces the RAM space to save backward metric and decoding delay time. With the reduced iterative decoding algorithm and the way to face some important problems mentioned above, a low complexity turbo decoder is implemented with fix-point digital processor (DSP) and the decoder is tested on the TMS320C6201EVM board. The test result shows the performance of the decoder is closed to that of float-point one simulated by MATLAB.