Based On The Nios Ii Digital Tv Receiver Synchronization System Design And Realization

What the dissertation completion is receiver synchronization system for Digital Television Terrestrial Broadcasting Standard of China. The design and realization is based on the Nios II Embedded Processor which is the System on Programmable Chip (SOPC). The realizations of all the system synchronization have been implemented based on Nios II which is the main hardware-platform that is grounded on the Altera's Stratix series FPGA(Field Programable Gate Array) chip EP1S80F1020C5. The dissertation firstly introduced the developing status of DTV, the whole structure introduction of the transmitter as well as the receiver in national standard. Focused on the arithmetic analysis and hardware architecture design of the synchronization system. Including frequency, sampling, symbol synchronization and process mode of the phase matching is discussed according to the characteristics of frame structure in national standard. At the same time, the theory and the hardware design of the residual frequency revision are introduced importantly. The academic simulation is also well done in this part. Besides, the dissertation provides detailed information on the hardware and software design of all-purpose algorithm in the synchronization system. The debugging results on the chip of the synchronization system are described in detail. In the end, the dissertation introduces the design of receiver synchronization hardware simulation-platform which based on the SPW(Signal processing workstation), and the simulation results. What I have mainly done in this dissertation is listed as follows:1. Read papers associated with the project, get familiar with the overall structure and principles of Digital Television Terrestrial Broadcasting Standard of China2. Complete the arithmetic design and simulation of the frequency, sampling and symbol synchronization as well as the residual frequency revision.3. Established the receiver synchronization hardware simulation-platform which based on the SPW. Complete the function simulation, analysis and validation of the synchronization system4. Complete the debugging on the chip of the system synchronization.