Font Size: a A A

Design And Implementation Of Distributed Flight Test System Bus And Verification System

Posted on:2008-10-03Degree:MasterType:Thesis
Country:ChinaCandidate:G L LiuFull Text:PDF
GTID:2208360212475403Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
The plane test system is often different from other test system, which usuallyinvoles the distributed framwork and is rigorous to requirement of outside bus, eg.real-time performance, higher bandwidth. Thus, several test systems both in and out ofhomeland are consistent to design and implement a special bus to achieve the goal, buttechnology of these test bus isn't open. It's impossible to extend its function, furthermore, which makes it difficult to integrate with other systems. Nowadays, Ethernet ispopular for data communication in Internet, its bandwidth is large and its application iswide; but its indetermination limits its usage in this area. So if there are some mannersto achieve the determinational communication on ethernet, the ethernet must make agood base to develop a feasible test system with its matural technics and low cost, evenrapid development.Here, dissertation mainly focuses on the important technology of outside and insidebus. Ethernet is a good choice for outside bus, which is cheap and has maturetechnology. Here introduces to time-share transmission mechanism in order to solveconflict problem of ethernet, which satisfied test system demand. In distributed testsystem, time-synchronization also is very important, former distributed system adoptedIEEE1588 to achevie their goal. IEEE1588 can satisfy rigorous demand, but whichimpeletmentation is difficult for the system without operating system. For the sake ofgetting better real-time performance and less jitter, the current system introduced FPGAinstead of MCU to implement. So, dissertation presents a new time-synchronizationprotocol. This protocol's implementation is easy and caters to project's demand.Another important part in distributed test system is transmission control map; it is coreof distributed test system. Transmission control map is a set of instruction executed byinside bus, which ensure sampling data can send to other card in time, finishedcollection and output function of test system.Finally, emluator's result proved thatdata-follow of Transimission Control Map is right.
Keywords/Search Tags:Distributed, FPGA, Ethernet, Real-time, Transimission control map
PDF Full Text Request
Related items