Research And Implementation Of Joint Detection In Td-scdma System

TD-SCDMA, which combines all the advantage of the time division deplex (TDD) with CDMA, is one of the three main standards of third-generation mobile radio system. Furthermore, it makes use of many advanced techniques, such as smart antenna, joint detection (JD), and so on. So, TD-SCDMA is the most efficient in using the spectrum in the three main standards.Joint Detection is one of the key techniques in TD-SCDMA system, and it is based on multi-user detection.Joint detection can reduce or eliminate the multi access interference (MAI), inter symbol interference (ISI) and Near-Far effects, simplify power control, reduce power control precision, and remedy the negative influence caused by the nonideal relativity of the orthogonal spreading code. Consequently, joint detection technique can improve the system performance, increase the system capacity, and extend the cell coverage.The character of the physical layer procedures for TD-SCDMA system is introduced and then Chapter 2 explains the joint-detection model for the uplink of TD-SCDMA system. A stydy has been made on the three kinds of linear joint detection algorithms inChapter 3. Then the performance and complexity of the three algorithms has been analyzed. In TD-SCDMA mobile redio system, joint-detection is equivalent to soling a least squares problem with a block-Toeplitz system matrix. By extending this matrix to a block-circulant matrix, it is possible to block diagonalize the matrix with Fast Fourier Transforms (FFT). In the last of Chapter 3, Simulation results and computational requirement figures for joint detection algorithms using FFT is presented.Chapter 4 introduces the tools using in the hardware implementation of joint-detection algorithm. And then the signal processing scheme for TD-SCDMA system is benn presented. Then the detail of every module for joint-detection algorithm is been described.Chpater 5 focus on the testing platform for joint-detection ASIC designing. The data exchange interface between DSP and FPGA is described in detail.