Based On The Rapid Owned Blocking Density Estimates The Layout Optimization |
| Posted on:2007-10-23 | Degree:Master | Type:Thesis |
| Country:China | Candidate:Y Xin | Full Text:PDF |
| GTID:2208360185497280 | Subject:IC design and manufacturing process |
| Abstract/Summary: | PDF Full Text Request |
| A placement optimization algorithm is developed in this paper using a probabilistic congestion estimation model proposed in the literature. The congestion estimation obtained from a placement allows us to consider a balanced optimization objective consisting of total wire length and routing congestion. A simulated annealing algorithm is designed to search the placement with a cost as lower as possible. The proposed algorithm is tested by a LDPC design example. Experimental results show that this algorithm can effectively reduce the total wire length and routing congestion with fast runtime. |
| Keywords/Search Tags: | Congestion, Placement, Routing, Simulated Annealing |
PDF Full Text Request |
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