The Ultra-large-scale Change Interconnects In Integrated Circuits

As technology scales, understanding semiconductor manufacturing variation becomes essential to effectively design high performance circuits. Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise. Conventional circuit techniques typically represent the interconnect and device parameter variations as random variables. However, recent studies have shown that strong spatial pattern dependencies exist, especially when considering interconnect variation in chemical mechanical polishing (CMP) processes. Therefore, the total variation can be separated into systematic and random components, where a significant portion of the variation can be modeled based on layout characteristics. Modeling the systematic components of different variation sources and implementing these effects in circuit simulation are key to reduce design uncertainty and maximize circuit performance. In this thesis we attempt to study this problem with distributed system theory.After reading large numbers of related literature, we first presented three methods for interconnect parametric uncertainty in this thesis. The first is named GETA. The technique models the stochastic response in a finite dimensional Hilbert space in terms of orthogonal polynomial expansions. Second, we present a Linear Fractional Transform (LFT) based model for interconnect Parametric Uncertainty. This model formulates the interconnect parameter uncertainty as a repeated scalar un certainty structure.The most primary achievement we get is that we present a simple but effective method called stochastic finite element method. Supposed stochastic variations are perturbed in a small range, we can get a nonlinear equation of these stochastic variations by using a Taylor series or a Neumann series expansion of the system matrix. The application of perturbation techniques translates this nonlinear equation into a pair of constant linear recursive equations. Then we have wrote a paper "Stochastic Finite Element Method for Interconnect Including Variational Analysis" which has been contributed to 1 lth Asia and South Pacific Design Automation Conference.