Digital Video Decoder Chip Design And Testing

The mission of this project,which is the design and test of decoder chip for digital vidio,is completed. It is included with analysing arithmetic,programing VerilogHDL code,simulation,synthesis,testifying it in FPGA and so on.The complete digital system is composed with several blocks such as Y/C divided circuit,digital phase locked loop,chroma demodulation,resample filter and the translating from YUV to ITU-R BT601. Firstly,it,some correlative theory of digital TV signal, is presented in the first and second chapter.Secondly,some EDA tools are simplely introduced in the third chapter. Thirdly,the paper has expatiated the process of luminance_ chroma deviding and it's simulaion result in the fourth chapter.Fourthly, the paper has expatiated the design of resample and line interpolation and it's simulation result.Finally,it has introudced how to testify the logic in FPGA. The main jobs have been completed as follows: ●Reading some papers. Understanding the principle of the system ●Stipulating for the frame, interface and subblock_dividing of the system ●Completing arithmetic design,simulation and result analysis for luminance_ chroma deviding and resample subblocks ●Programing Verilog code for the subblocks ●Designing of the testing circuit board for FPGA...