Research And FPGA Implementation Of Key Module For SAR Imaging Algorithm

Synthetic Aperture Radar(SAR)is an active microwave remote sensing imaging radar.It can improve the vertical resolution of the beam by processing the Doppler frequency domain.With the rapid development of SAR systems,radar will receive massive echo data and need to complete data processing in real time.Traditional digital signal processors have lost its advantages gradually,and with the development of VLSI,The performance of FPGA has been greatly improved,and its role in SAR signal processing is getting more and more important.Because of above problems,this paper studies the SAR imaging algorithm and FPGA implementation.Firstly,the basic theories of SAR imaging are briefly introduced.And the principle of pulse compression is introduced.Then,the scene of the airborne SAR scanning the ground point target in side-view strip mode is modeled,the echo model is analyzed in the time domain and the echo data is generated.The Range Doppler(RD)imaging algorithm is modeled,and finally the SAR echo data was processed by the RD algorithm.The results show that the imaging effect of the SAR imaging system model built in this paper is good in the case of positive side view.In addition,the hardware circuit design and implementation of the pulse compression module in the RD algorithm is completed.Firstly,the overall hardware architecture of the pulse compression module is designed,and then the key modules-Fast Fourier Transform(FFT)module and complex multiplier unit are designed.Then the decimation-in-frequency FFT of the radix 2~2 algorithm based on serial butterfly unit is introduced.And a 1024-point FFT is implemented.And a CSD constant multiplier and mutilple constant multiplier are designed for a special set of twiddle factors.In addition,a 3-multipiler-5-adder complex multiplier is designed.Finally,the FFT module and the pulse compression module are synthesised.From the synthesis results,it can be seen that the clock frequency based on the serial butterfly unit structure FFT is improved by 44.8%compared with the conventional structure,and the slice resource is saved by nearly half.Finally,the hardware design and verification of the range cell migration correction module is carried out.The range cell migration correction module uses the sinc function to implement the interpolation method.Comparing the simulation results with the results calculated by Matlab,the correctness of the hardware design function is verified.The hardware module implemention the sinc interpolation function well.