Dvb-s Channel To Receive The Research And Implementation Of The Chip-byte Processing Chain

We are in an era economy is based on the knowledge that impacts people's livelihood with unprecedented importance. Broadcasting network by satellite, with its wide frequency band and vast overlay, acts as an excellent medium for the widespread of information. Concurrently, accompanied by this economic torrent with knowledge, a digital revolution breaks out, leading to the full development of a series of modern technologies like IC technology, Information-Processing technology, Communication technology, etc., and emphasizes itself in the process of digital TV's rapid progress. The IC chip for digit TV receiver through DVB-S channel, is precisely the combination of these advanced technologies. The main work of the paper implements the byte processing part in this chip.The circuit to fulfill the byte processing function includes all parts between the modules on convolutional decoding and transfer stream de-multiplexing, consisting of the modules on data de- interleaving, RS decoding, data de-scrambling and format transforming.The rapid progress of semi-conductor technology on deep sub-micro and nanometer scale announces the SOC era of IC design. Since the SOC design excels multi-chip in speed, power consuming and cost, it is of extreme importance to develop SOC design in future IC industry. Moreover, as the scale expands, some minor factors in traditional ASIC design become crucial in SOC design, even decide its success. In order to use those functional modules in SOC also, it is necessary to take these 'minor' factors into account.The paper consists of eight chapters. The first chapter summarizes the characteristics of digital TV and DVB specifications, and introduces the relating concepts of ASIC and SOC design.Chapter two gives a simple explanation on the framework of digital TV receiver system.Chapter three sketches the structure of the chip as DVB-S channel receiver, and introduces the main parts of DVB-S channel sender.From the fourth chapter on, the paper explains the study and implementation on the byte processing part module by module. The fourth chapter shows the principle andthe ASIC implementation of data de-interleaving.Chapter five thoroughly discusses the algorithms on encoding and decoding RS code, and implements the ME algorithm with ASIC.Chapter six studies characteristics and implementations of pseudo-random sequence generator and data scrambling, and fulfills the de-scrambling function with ASIC.Chapter seven puts forward the scheme to adjust data rate, discusses the design in multi-clock circumstances, and implements the multi-clock application on adjusting data rate for DVB-S.The last chapter studies the characteristics and methods of SOC design, and advances the scheme of byte processing part in DVB-S channel receiver for SOC design.The paper compares some algorithms on RS decoding, makes improvements based on the ME algorithm, removes the modifying step in decoding truncate RS code, corrects unsuitable statements in the related papers, and parameterizes the RS decoding module, reducing its area by 20%. The paper overcomes the signal integration problem in multi-clock design, greatly lowers the phase jitter without area increase, introduces PLL to adjust rate for the first time, and parameterizes the module. Finally, relating to the trend of SOC design, the paper analyzes the IP reuse method, pointing the direction to improve the performance and reduce the cost.