Design And Realization On Traffic Cotrol Mechanisms Based On NetworkProcessor

With the development of Internet technology, the network services are more and more abundant and complex, which make the net traffic increasing. As the basic of network service, traffic controls with intellgence become more and more important. But, how to control the traffic effectively is the bottleneck of network traffic control because of the heavy and nonlinear characteristics of network traffic. In order to improve the packet processing efficiency, the traffic control mode has changed from software control mode to the mode combining software with hardware control model. The network processor is a special integrated circuit designed for network applications, which has good scalability and the high-speed packets processing capability. Network processor extends the classic store-and-forward working pattern of router to store-processing-forward pattern, which can be used in traffic control mechanisms for high-speed packet processing. This dissertation researches the software model and the related hardward including the architecture and characteristics. The parallel-processing capability of network processor is researched especially.This dissertation proposes the traffic control mechanism based on the network processor. The key algorithms of the mechanism are designed and realized. Used the diffserv model, the proposed traffc control mechanisms include four parts: packets classification module, marking&shaping module, queue managing module and queue scheduling module. The related algorithms in the four modules are researched. The suitable algorithms are selected for each module in order to adapt the traffic control mechanism characteristics. The strategy combining software and hardware is used to classification the packets quickly and effectively in packets classifiying module. STRCM algorithm is used to mark the traffic in marking&shaping module. The weight random earliest detetion algorithm is used to avoid congestion in queue managing module. The low latency queue algorithm is used to assure the priority of traffic with low-latency requirement and guarantees minimum bandwidth and traffic independence. The proposed traffic control mechanism combines the characteristics of software and hardware, which has flexibility of software and the efficiency of hardware.In order to analyse the performance of traffic control mechanisms, the second generation network processor of Intel, IXP2800, is choosed as the main hardware platform. Intel SDK 4.2 Workbench Developer is choosed as the software simulation platform. The related packets processing modules in traffic control mechanism are realized separately using micro-engine in network processor. The parallelism of algorithms is realized by multi-thread mechanisem, which can improve the efficiency of packets processing and make the traffic control mechanism module and scalability. Experimental results show that the proposed algorithm can classify the traffic, mark and shape the traffic, manage and schedule the queue. Otherwise, the algorithm can satify the requirement with the 10Gb/s traffic and improve the performance of packet processing, which can resolve partly the bottleneck problems of high-speed paket processing. Experimental results also prove the effectiveness of proposed traffic control mechanisms.