Based On The Dlx Architecture Microprocessor Core Design

This paper introduces the design and realization course of a microprocessor core based on DLX architecture. Our purpose is to develop a basic platform of CPU microarchitecture research, which providing architecture researchers a basic hardware and software environment, based on which, they can perform in-depth research of microprocessor architecture concepts and technologies. We realized a microprocessor core with the help of ModelSim SE 5.6 developing platform, in Verilog HDL.We analyzed the DLX architecture which was brought out by Hennessy and Patterson in Computer Architecture: A Quantitative Approach. Though comparison to other micro-processor architectures, we chose DLX architecture as our goal, and designed a DLX instruction set.Under the DLX instruction set, the design flow of a microprocessor includes functionality organizing, logic designing and realization technology. We discussed the design flow of DLX microprocessor, and bring forward the detailed design of the core. We adopt an inter-locked pipeline structure in our 5 stage CPU organization, which means when there are data hazards and structure hazards in the instruction sequence, we use the method of insert stall cycles in pipeline.We realized a 2-level storage system including a cache memory, a main memory and the memory control interface between the storage system and the pipeline core. We provided a simulation realization of the main memory with Verilog HDL. We also provided a interface to access the external memory chip.We accomplished the RTL level description of the DLX microprocessor core in Verilog, and completed functional verification and pipeline performance analysis on the ModelSim SE 5.6 platform.The achievements of this paper have important practical and realistic significance to computer architecture research, CPU designing, researching and teaching.