LTE System Synchronization Of Low-power FPGA Implementation

LTE as a mainstream technology from 3G to 4G has been got more attention, and its related industries have also ushered in a new era. In the LTE system, synchronization is an important means of recovering data correctly in the terminal.In this paper, in-depth study the LTE system synchronization technology.Compared the complexity and performance of the existed algorithm and proposed some improvements. Adopted the fragment of time-domain algorithms to detect PSS and SSS signal by sliding correlation, The FFT module be designed to complete signal conversion from frequency to time domain. This design uses Xilinx’s Virtex7 FPGA chip to build the hardware platform. Find the position of PSS signal in OFDM firstly;Then track the location of the SSS signals based on the type of CP, fulfill SSS signal detection; Finally, identified the cell ID quickly and accurately. Fulfill the synchronization between UE and base station in the time and frequency.Synchronization algorithm used Verilog HDL to build model in hardware implementations. Functional simulation,logic synthesis,and RTL implementation used Xilinx software tools. By optimizing algorithms and constraining code to reduce resources occupation in the FPGA, further reduce the power consumption of the chip.Finally, by using Matlab and ChipScope to simulate and grab signal on the chip in synchronization system, compare the software simulation and hardware results. The results showed that the design completed LTE system initial synchronization and resource optimization task. At the same time reduced the complexity and power consumption.