Evolvable Hardware Platform

Evolvable Hardware (EHW) simulates the biological evolution in nature. It can evolve towards a target function with the guidance of the evolutionary algorithm (EA). It can be promising in the fields such as automated design of circuits and adaptive systems. Being developing for almost 20 years, EHW is still seeking for better platform with different granularity. Solutions for better evaluation strategy, higer evolving speed and larger evolving scale are still to be studied.Based on self developed FPGA technologies, this thesis focuses on solutions for muti-level EHW platforms, provides reconfigurable capacity in different granularities, proper EA and tool chains. Solutions for LUT (look up table) level, module level, on-Chip level and network level EHW platforms are proposed here.Firstly, based on the FDP FPGA chip designed on our own, an LUT level EHW platform is proposed. An EA that can keep evolving from stagnated is provided on this platform. A new structure of reconfigurable circuit is presented, which can be used for evolving combination logic and sequential logic. And an adaptive evaluation algorithm is used. The experiment result shows that the proposed EHW platform outperforms the previously proposed platform by 10 times of evolving speed.Secondly, module level EHW platform is studied. And the emphasis goes to its key requirement:the partially and dynamically recofonfigurable (PDR) hardware. A novel Transfer-Bus macro is proposed to provide PDR capacity. The tool chain for PDR system design is also provided. A PDR image filter was developed and the result shows that less than 50 ms are needed for modular replacement, meeting the main requirements of the module level EHW platform.Thirdly, to further improve the speed of evolution, an SOC chip is designed to build an on-chip level EHW platform. The SOC chip proposed here was integrated with a CPU IP and an FPGA IP. A fast self-reconfiguration technology was introduced to accelerate the reconfiguration; according to the requirements for different fitness evaluation strategies, a dedicated data-exchange interface was designed to provide a more flexible and robust platform; to accelerate the EA, a hardware random number generator (RNG) was designed to provide random numbers. Experiment results show that these proposed technology speeds up the whole platform in an order of magnitude.Lastly, to provide a platform with better modularization capacity, a network level EHW platform is proposed. The main solution for network level EHW platform is a reconfigurable "network on chip" (NOC) prototype. The key modules of the NOC chip are designed to provide two features:reconfigurable network topology and reconfigurable nodes.Simulation and FPGA validation show that the proposed NOC prototype functions correctly and the network can support a maxium throughput of injecting 0.7 packets of data per node per cycle in a set pattern.