.600 V The Vdmos Power Device Technology Optimization

The optimization of high voltage VDMOS process is studied in this paper.Threshold voltage (VGS(th)) before optimization is higher than-design target. Gate oxide thickness and doping concentration (NA) of p type body are related with VGS(th). Through design of experiment, VGS(th) can be reduced without any gate oxide thickness loss by adjusting the implant dose of JFET, P-Body and N-Plus. Also, MOS channel function can be improved with lightly doped tilted implant applied in N-Plus. VGS(th) meets target after optimization with none effect to breakdown voltage, on-resistance and drain leakage current.Zero layer is needed to form alignment mark for following lithography layers. The experiments show it can be replaced by the field oxide structure which matches the requirement of alignment mark. It can be recognized by the lithography alignment system. The production cycle time and cost of this product are reduced after removing zero layer.To improve product reliability, Polyimide is coated on device surface as passivation layer. It was found peeled up at the corners of die. Base on analysis of Polyimide formation and experiment, this issue is resolved by setting Polyimide develop time shorter.After the process optimization, the device yield is higher than-95%, and cost down over 10%. The product, technique and process described in this paper are all from fab manufacturing. It can be used as a reference for people who study or produce similar high voltage VDMOS.