The Dvb-t2 Standard Ldpc Encoding And Decoding Dsp To Achieve

The standard of DVB-T2 (the second digital terrestrial television broadcasting standard of European) is a new television broadcasting standard made by DVB organization and improves at least 30% channel capacity than DVB-T.It introduces a new technology of modulation and coding and takes advantage use of terrestrial spectrum to deliver video and data services for fixed, portable and mobile devices.The error correction coding of DVB-T2, the same as DVB-S2 is LDPC coding combined with BCH coding. This makes DVB-T2 deliver a robust signal in the environment with a lot of noise levels and interference.LDPC channel coding of DVB-T2 standard is one of most important achievements in coding. Not only is the performance of LDPC close to Shannon limitation but it also has low calculating complex. This thesis researches the coding and decoding algorithms of LDPC on the application background of DVB-T2 standard and realizes them on DSP.This thesis first compares and analyzes BP, log-domain BP and Min Sum decoding algorithms and choose Min Sum algorithm as the LDPC decoding algorithm of this DSP realization.Then for saving check matrix this thesis proves the multi-stripe part of check matrix can be translated into many quasi-cyclic sub-matrix through simulation of MATLAB on the condition of without changing the performance of decoding algorithm. So this thesis offers a new method to save check matrix. It only saves the first row of every quasi-cyclic matrix. In this way the memory needed is three hundred and sixtieth of the total non-zero elements.In next step this thesis studies two scheduling decoding algorithms. They are RMP and SMP. And give the C language coding of the two scheduling decoding algorithms. In order to enhancing the execute speed I optimize C code combined with feedback message of CCS Compiler by software pipelining, accessing with long word, using intrinsic etal.At last, the processing board of SEED-VPM642 is configured, the C code is downloaded to processing board and debuged, and the decoding performance of different rates for LDPC code is offered.