The Design, Based On The Usb Interface Of The Ber Tester

BER(Bit error rate) is an important indicator of the reliability of a digital communication system to transmit information. Bit error rate tester is an important tool for testing BER of a communication system, and a major equipment for communication system performance test and fault diagnosis. Although there are many error rate testers for sale and they have excellent performance, they are very expensive. In addition, the communication system developed by our group have special requirements for interface and portability of the BER tester, so I developed a bit error rate tester during the communication system development to provide the bit error rate information for system debugging.This thesis describes the implementation of error code tester. The error tester consists of two parts: Windows applications and data transceiver board. Data transceiver board has a USB interface and a FPGA chip. The USB interface is between the FPGA and the PC, providing a secure, high speed data transmission interface, and making the data transceiver board be hot swappable. FPGA makes serial data transceiver and realizes duplex reading and writing operations on USB endpoint FIFO caches. Functions achieved by the windows application are as follows: generating pseudo-random codes; writting testing datas to the USB endpoint cache through the USB interface when a user sends a"send"request; reading data in the USB endpoint cache into the computer when the user sends a"receive"request, calculating and displaying the error rate. In order to make the application have an ability of duplex data reading and writing, we use multi-threaded programming techniques to improve the application's ability of corresponding external events.In order to take advantage of the hardware and software resources of PC, the function of error bit rate calculation and displaying is done by the Windows application. This will not only provide users with high-quality observation interface, but also simplify the FPGA logic design, greatly cut the cost and time.