Analysis And Optimization Of Multi-core Multi-threaded Processor Memory Access Parallelism

Since Intel Corporation produced the world's first general purpose microprocessor Intel 4004 in 1971, the microprocessor has gone from single core to dual core, and then multicore,even many-core with the development of technology and research on architecture design. Multicore, multithreaded processors have become the mainstream microprocessor.However,while the multi-core and multi-threaded technology improves the performance of microprocessor,the memory system has also been put forward higher requirements. Thus,the performance of memory systems has become an important factor restricting the further improvement in performance of multicore, multithreaded processors.A memory controller is an very important part of processor system design,which greatly affects memory access speed. On multi-core multi-threaded processor integrates multiple memory controllers that can be executed in parallel, playing an important role to alleviate the pressure of the huge amount of data's access. However, in a multi-threaded application environment, there are still bank conflicts. In order to alleviate the bank conflicts existed in multi-core multi-threaded processors, this paper analyzes the memory access parallelism of multi-core multi-threaded processors,and selects the address mappng scheme in memory controller as the direction if optimal design.On the base of analysis of memory system architecture, especially the structure and working mechanism of DRAM,we make study on the characteristics of the multi-threaded application's memory access,espacially on the bank parallelism with the use of DRAMsim2 experimental platform. Finally, this paper analyzes the causes of bank conflicts, and provides a hash optimization algorithm which is based on the address mapping scheme to optimize the memory access parallelism of multi-core and multi-threaded processor,and design an experiment to give verification. And then using the measured stream test procedures, the results show that under the 64-thread memory access bandwidth upgrades from 5.88 GB / s to 14.24 GB / s, reaching optimal design goal.