Co-optimization For Soc Test Based On Hybrid Genetic Algorithm

To test SOCs efficiently is urgent demanded by the development of integrated circuits technology, and testing a chip in short time is an expression of efficiency. SOC testing is time consuming because the ability to test IP cores synchronously is weakened by the scarcity of test resources in SOC which based on the technology of IP core reuse. On the basis of this background, minimizing testing time under the conditions of limited testing resources becomes the objective of optimization for SOC test. In a typical SOC test framework, to optimize the test wrapper, test access mechanism or test scheduling can shorten the testing time for SOCs, and solving these problems in conjunction will certainly achieve greater effectiveness. Taking this principle as a breakthrough point, the problem of co-optimization for SOC test is studied in this paper and a solution based on hybrid genetic algorithm is presented.According to the characteristics of IP core test, a mathematical model is set up to create a mapping between genetic space and solution space in this paper. With the aid of an effective heuristic recursive strategy, the fitness function is designed to reduce time consumption when chip is tested with the same IP core sequence. A flexible TAM architecture is adopted in this paper, thus the TAM which assigned to cores could be adjusted to an appropriate size. Therefore the test resource wastage in prior researches can be prevented. On the basis of these works, different sequences of the test of IP cores are generated by genetic algorithm and the final SOC test solutions is selected by the genetic manipulation of superiors to win and inferiors to be eliminated. The proposed method was implemented in C and applied to ITC'02 SOCs Test Benchmark. Experimental results show that lower testing time was obtained by this new method compared to other methods.