A Cmos Low Dropout Linear Regulator And Design

As more and more portable products, there are higher requirement on product features, performance improvement, power management. In the development of battery-powered portable electronic devices such as mobile phones, MP3, PDA, GPS and other low-power products, if the power system design is unreasonable, it will affect the entire system architecture, product feature set, the software design and power allocation framework. In most cases, portable products are battery-powered, internal (ie, battery back-end) power management with DC/DC and the LDO implemented in two ways, each with advantages and disadvantages. Normal status, DC_DC module can provide a stable voltage to the system and maintain its high conversion efficiency, low heat. Conditions in some applications, such as work in the light load conditions or when to RF power, DC_DC quiescent current and switching noise becomes greater. Switching Power Supply (DC_DC) and low dropout linear regulator (LDO) of the combined system can be greatly improved system performance, while providing a high-precision power supply voltage. CMOS LDO just meet the conditions in these applications, power requirements, CMOS LDO with low quiescent current, low noise, high PSRR (power supply ripple rejection ratio), and low Dropout Voltage.This paper presents a low-dropout regulator (LDO) for portable application. The low-dropout regulator based on a precision CMOS reference, which is comprised of band-gap and has small temperature coefficient. With Chopping architecture to eliminate the offset introduced by AMP and package sift introduced by the chip package. Furthermore, Completing the traditional voltage-mode miller compensation with a current-mode capacitor multiplier enhances the effects of the Miller capacitor. Combination the improving Miller compensation and active loading compensation method improve the system unit gain bandwith and phase margin. The proposed LDO's stability is independent of the load or the Equivalent Series Resistance(ESR)of the off-chip capacitor. The chip design is based on 0.6um CMOS mixed-signal process. The simulation and experimental result show that the line and load regulations are less than 1mV and 5mV (with parasitic parameters) respectively. The dropout voltage is only 300mV at 150mA output current when output voltage is 2.8V. The output noise is 80 uVRMS when frequency range from 1HZ to 100Khz. Quiescent current is only 25uA.