.1553 B Bus Interface And Fpga Implementation

MIL-STD-1553B, the America military data bus standard, is an aircraft internal time division command/response multiplex serial data avionic bus standard. With the high reliability and agility, the multiplex transmission bus is widely applied in the airplane, warship and tank. The key to the 1553B bus system is to design 1553B data bus interface chip.After studying the MIL-STD-1553B protocol and design of foreign chip product, combining the presently rising EDA technology and the trait of large programmable logic device. The paper puts forward a project of designing the interface based FPGA.According to the detailed function of interface chip, this paper apply the Top-Down designing method to put forward the total design scheme 1553B bus interface. Then with the detailed implement of curcuit divide the structure. After the introduce the circuit design of analog receive& transmitter, primary introduce the design of BC/RT/MT terminal, then make sure the universal interface by a select signal, and also gives the design, simulation and test of the important modules. In the course of the design, critical technologies are applied, such as the Top-Down designing method;Digital phase-locked loop in code conversion;UART in serial communication .The design describe the design by VHDL, synthesis by synplify and realize it in FPGA. The result shows that the design implement three kinds of terminal functions, and it can process a variety of message communications in multiple formats, and have great function of detect error.At last, design the test system of bus interface chip, and select the Tms3201f2407 as the primary CPU. The test contain the self-receiver& self-transmitter of the CPU, and the RS232 serial debug to hence the intuition of test data, The result of validate indicates that the design in this paper is reasonable and right.