Dds-pll With Low Phase Noise Low Spurious Frequency Ensemble Study

This paper introduces a frequency source with low phase-noise and low spurs and the performance of the system.In the design DDS (direct digital synthesizer) and PLL (phase-locked loop) were used while DDS act as the reference of the PLL. In PLL phase detector integrates digital programmable pre-divider and divider, a MCU can control them expediently.The structure has the advantages of both DDS and PLL, and makes up the shortage of each other in a certain extent. So it can be used in the design.It is very important that the structure of DDS driving PLL is used in the design, using the structure the source has achieve hereinafter levels: the frequency rage is from 637 MHz to 701MHz, the step length is 0.5MHz, and frequency switching time is 20μs. The frequency locked time is 5μs, the phase-noise is-110dBc/Hz@10kHz, and the level of spurs is-70dBc. Every one of them is not difficult to realize, because they are easy to achieve using DDS or PLL. But as a whole, the performance is difficult to realize, because both DDS and PLL will be used, however, DDS and PLL can compose many structures, different structures will affect the realization of the performence. It is according with the need of the system that the author selects the structure of DDS driving PLL. Later the author has done some work to prove that using the structure the system can achieve perfect performance. And later the author has done an all-around design to the system and an optimization to the PLL and some analysis to realize the EMC of the system, all the work has contributed to the perfect performance of the source.The main characteristic of the paper is that all the levels were achieved and the system performs very well.