Research Into Key Technologies In Silicon-Based RF And Millimeter-Wave Frequency Synthesizers

With the development of wireless communication systems,the requirements for frequency synthesizers become more and more stringent.At the same time,the silicon-based technology is becoming more and more popular because of its low cost and high integration.In the design of millimeter-wave frequency synthesizers,as VCO operates at a high frequency and leads to a large divison ratio,this greatly increases the noise contributed by charge pump and Delta-Sigma modulator(DSM).Furthermore,the phase noise and tuning range of millimeter-wave VCOs are degraded as varactors and constant capacitors may dominate the loss of the tank.Consequently,frequency synthesizers working in RF and millimeter-wave band are usually of a poor jitter performance.This thesis makes an in-depth investigation into silicon-based RF and millimeter-wave frequency synthesizers,focusing on fractional phase-locked loops and key modules therein,such as voltage controlled oscillators(VCOs),frequency dividers,integer phase-locked loops(PLLs)and so on.The main research content of this thesis is divided into the following five parts:1.Design for low phase noise inverse-coupled VCO.Two current-reuse VCOs are inversely coupled through their tank,and form the inverse-coupled VCO.The proposed inverse-coupled VCO inherits the excellent phase noise performance of current-reuse VCO,and can realize differential outputs and reduce the interference of VCO to power lines and ground lines.In addition,phase noise of the inverse-coupled VCO is reduced by 3 d B due to the electromagnetic coupling.At the same time,the transformer formed by the inverse coupling also improves the quality factor of the tank,thus reducing phase noise.The prototype chip of inverse-coupled VCO is fabricated in 180 nm CMOS process,and area of the core circuit is 0.4 mm×0.32 mm.Test results under a 1.2 V supply voltage show that the tuning range is 2.88 GHz?3.61 GHz.At the lowest frequency and highest frequency,phase noise at the frequency offset of 1-MHz is-126.7 d Bc/Hz and-123d Bc/Hz respectively,and Fo M(Figure of Merit)is 188.1 d Bc and 190.7 d Bc respectively.2.Design for millimeter-wave implicit tripler VCO.An implicit tripler VCO topology is proposed.By combining the current injection transistor pairs in the traditional frequency tripling structure into the fundamental VCO,phase noise of the fundamental VCO is reduced due to the noise circulating mechanism.In addition,since the current injection transistor pair becomes part of the fundamental VCO,it does not need to consume an additional current,thus saving the power consumption.The proposed implicit tripler VCO can output a fundamental wave and a third harmonic at the same time,and the fundamental wave VCO is of a low phase noise.Test results of the chip prototype fabricated in 65 nm CMOS process show that the output frequency range is 33.68 GHz?40.11 GHz(17.4%).The DC current consumption obtained from the test is 4.1 m A at the lowest frequency and 4.9 m A at the highest frequency,respectively.At f_min and f_max,the phase noise at 1-MHz frequency offset is-101.2 d Bc/Hz and-97.9 d Bc/Hz respectively.3.Design for wide-band injection-locked divide-by-2 frequency divider.A distributed high-order resonance tank is proposed,where the phase shift generated by the zero and pole frequencies in the input impedance of the tank can cancel each other across a wide frequency band,resulting in a zero-phase-shift plateau.The influences of the inductors and capacitors of the high-order tank and their losses on phase responses and amplitude responses are analyzed,and the condition when zero-phase-shift plateau occurs is obtained.According to the theoretical derivations and the verification of simulation results,the detailed design flow of the proposed wide-band tank is presented.Based on the above analyses and simulations,a wide-band injection-locked divide-by-2 frequency divider is fabricated in 65 nm LPCMOS process.Operating under 0.7 V supply voltage,the frequency divider consumes 7 m W DC power.When the injected signal power is 0d Bm,the locking range is 13 GHz?33 GHz,and the relative locking range is 87%.When the input signal power is lowered to-6 d Bm,the frequency divider still has a relative locking range of 69.6%(15 GHz?31 GHz).4.Design for low jitter integer PLL.The traditional charge-pump based PLL has the disadvantages of narrow bandwidths and large spurs,while the subsampling type-I PLL has the advantages of low phase noise,small spurs and large loop gains,but the locking range is very small.Therefore,the two can be combined to form a phase-locked loop with a dual-loop topology,so as to avoid their respective shortcomings and make use of their respective advantages.The main loop adopts a charge-pump based loop,which has a small loop bandwidth and a large VCO gain,can realize frequency and phase capture,and suppress the noise contribution and reference spurs of the charge pump at the same time.The auxiliary loop adopts a subsampling type-I loop,which has a large loop bandwidth and a small VCO gain,which can suppress the phase noise contribution of VCO and have small reference spurs.Analysis shows that the-3 d B bandwidth of noise transfer function for charge pump is determined by the cross-point of gain for the main loop and for the auxiliary loop,which is much smaller than unit-gain bandwidth of the main loop.The noise transfer function bandwidth of VCO is determined by the auxiliary loop.Therefore,the noise contribution of the charge pump and VCO can be adjusted separately and are suppressed at the same time.The dual-loop integer PLL designed based on the above theory is fabricated and tested in 130 nm CMOS process.The integral RMS jitter of 1 k Hz?100 MHz is 1.36 ps and the corresponding Fo M is-229.8.5.Design for low jitter cascaded fractional PLL.The fractional PLL adopts a two-stage cascade structure,in which the first stage is a subsampling dual-loop integer PLL and the second stage is a conventional fractional PLL.Firstly,the method of increasing the length of DSM sequence to reduce fractional spurs is analyzed.By delaying the overflow bit of each stage in the conventional DSM and feeding it back to its input,the DSM can achieve the maximum sequence length for any inputs,and the sequence length is of an exponential relationship with the number of stages.Secondly,the relationship between the quantization noise of DSM and the frequency of the reference clock is deduced.The results show that increasing the frequency of the reference clock can effectively reduce the quantization noise of DSM.The subsampling dual-loop integer PLL is used as the reference clock frequency multiplication circuit,which does not introduce too much additional noise while improving the frequency of the reference clock.Finally,the VCO adopts an implicit tripler VCO topology,which can output the fundamental voltage and the third harmonic voltage at the same time.The fundamental voltage is fed back to the PFD for the locking of the fractional PLL,while the third harmonic voltage is used for the final output of the fractional PLL.As VCO operates in the fundamental mode,it can obtain an excellent phase noise performance.A conventional fractional PLL and a cascaded fractional PLL are fabricated in 28 nm CMOS process,with the reference clock being 40 MHz and the center frequency of the PLL output being 27.6 GHz.Simulation results show that the integral RMS jitter of 1 k Hz?10 MHz is 980 fs for the conventional fractional PLL,while the corresponding integral RMS jitter is reduced to 290 fs for the cascaded fractional PLL.