Design Of High-performance Pseudo Random Number Generator

In this paper, a high-performance pseudo-random number generator is designed. As an important part of the encryption system, this design can provide high-performance pseudo-random number for DES, AES or other encryption algorithms, thus ensures the reliability of the SoC system.The random seed is produced by digital circuit, then the bias corrected technology is used to balance the random sequence of 0 and 1, at last, MD5(Message-Digest Algorithm 5) algorithm or optional LFSR(Linear Feedback Shift Register) method is used to enhance the randomness of sequence. The generation rate of pseudo-random number can be regulated by configuring the XOR series register or the MD5 compression ratio register. The interface part of this design is based on AHB protocol, so this design can be used as IP in ARM-based embedded system.Firstly, VERILOG HDL is used for hardware description of the system. Secondly, the simulation tool VCS and the debugging tool VERDI are used for pre-simulation and the FPGA are implemented for post-simulation. Thirdly, the performance of the generated pseudo-random number is evaluated by NIST (National Institute of Standards and Technology) and Diehard international standard testing set. Finally, DC and Formality are used for synthesis and formal verification. Results show the pseudo-random number generated by this design has passed all the NIST and Diehard international standard testing set, thus has a good random performance.