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Low Power Multiplier Design And Implementation Based On SRPG

Posted on:2011-09-03Degree:MasterType:Thesis
Country:ChinaCandidate:L ZhaoFull Text:PDF
GTID:2178360308985607Subject:Software engineering
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Facing with the challenge of power density in deep sub-micron technology, power became a new catchword in the semiconductor world, sophisticated and aggressive approaches such as Multi-Voltage and MTCMOS which used to reduce power were widely used in the mobile devices which could reduce the energy consumption significantly in the standby mode. Using advanced methodology and new additional low power standard cells, the State Retention Power Gating (SRPG) could keep data while the power is shut down, so the research work on the effective and great potential method is significant.We explore different strategies in low power design including the latest available low power techniques relying on sufficient analysis and comparison, especially on the SRPG. A module-level low power design is accomplished base on the theories before and the United Power Format (UPF) with Synopsys co. Eclypse design flow, the major research work of this article include as follows:The thesis present the VLSI design methodology for low power design, including the advanced methodologies newly apposed in the world, established the foundation for the low power design research in theory.Then, we designed a new standard cell library called Power Management Kit (PMK) which using in the Coarse Grain power gating approach while accomplished the long-gate standard cell library for contrast. The PMK is successfully used in the Multi-Voltage & MTCMOS Design, the long-gate standard cells reduce 15% leakage power at a cost of 1~3% dealy and 8% dynamic power increasing contrast with the common standard cell.Furthermore, review the defect of existing cell modeling for delay and noise analyses, the method about PMK cells modeling with enhanced Lib format relying on current source model were given. We also extend the existing noise model to accurately handle dynamic delay.In the end,explore the low power semi-custom design flow using SRPG with UPF. Implemented low power design in 90-nm CMOS technology empolying different approaches, including strategies and standard cell libraries. The comparison results showed that, based on the UPF, by utilizing the artificial PMK could exceed approximately 30% leakage power reduction in the standby mode.
Keywords/Search Tags:Low Power Design, SRPG, UPF, Standard Cell, Current Source Model, Low Power Synthesis, Rush current
PDF Full Text Request
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