Design And Implementation Of Multi Mode AES IP Core Base On AXI Interface

AES (Advance Encrypt Standard) is an encryption algorithm through the levy election set to replace DES (Data Encrypt Standard) by National Institute of Standards and Technology (NIST) in 2000. The algorithm of AES is called RIJNAEL, it is flexible to implement either hardware or software, and it is security and strong and able to adapt to very different working environment, it becomes a research hot spot since its birth.This thesis designed an AES IP core with low hardware cost and good process ability, and it is compatible with many different modes to work in different security level, it's suitable to use in SoC for handheld device. This IP core is starting from the algorithm design, using low cost and reuse method in each step from the AES algorithm. In SubBytebytes, using Galois field calculation instead of LUT; In Mixcolumns, using all XOR gates to implement through the deformation of the matrix; In encryption and decryption, using equivalent decryption method to achieve the greatest degree of hardware multiplexing; In compatibility, there are four operating modes, including two feedback and two non-feedback modes to accommodate different encryption requirements. As a SoC design, an on-chip bus interface is necessary, in this thesis, the latest ARM AXI (Advanced eXtensible Interface) bus is adopted. It has high bandwidth, low latency and it is flexible to design. It has become the most widely used on-chip bus standard in SoC. As a slave device, the IP core includes AXI interface, two non-symmetrical FIFO, DMA interface and AES encryption core. AXI interface is designed using state machine design, minimizing hardware cost, and the low power interface is using, its gate count is only 992.By using Synopsys VCS and Novas Verdi, under the Synopsys platform VMT (Verification Modeling Technology), AES IP passed the functional verification. FPGA verification is passed through under Xilinx VIRTEX5 series XC5VLX330T chip. Using 90nm technology to complete synthesis by Design Compiler, the total gate count is 24.3K, under the frequency of 133 MHz, its throughput is about 1.4Gbps. Therefore, it is fully capable for communications needs of handheld device.