Research And Design Of High Performance Configurable Processor For Intra-predict

This paper describes the design of an Application Specific Instruction Processor based on Transport Triggered Architecture which is simple, modularized and programmable. Thus the TTA can overcome the limitation of current ASIP and Micro Processor Unit, and could get the processor which satisfies target application as fast as possible.TTAs were developed to avoid the problems that exist in VLIW architectures. The complexity of the bypass network is reduced by moving the RFs into the same architectural level as the FUs. TTA hybrid pipeline allows for maximum scheduling freedom.This work implements the design of processor for H.264 Intra-predict and IDCT based on the structure of TTA on Move Framework platform. The main work includes configuring the Architecture description, analysing instruction level and data transport level parallelism and making a balance among execute cycles, area and power.This work focuses on researching a design methodology from top down for H.264 Intra-predict and researching a design methodology from buttom up for multiple algorithms. The simulation results show that the powers and areas of optimum TTA processors have both reduce about 50% than the initial one without a effect on execute cycles. Comparing with general processor such as TM320C5510, execute cycles of the TTA processor on H.264 intra-predict has reduced 61.35% and execute cycles of the TTA processor on multiple algorithms has reduced 141%.