| As people becoming increasingly demanding on perfermece, Especially for engineering high-density computing,single-processor system has not satisfied people's requirements enough. Along with the development of IC process technology, multiple processors technology has become the trend of next generation IC design. The key of MPSoC design is How to improve the efficiency of communication between multiple processors. In the small and medium-scale multi-core system design, we ususlly choose on-chip bus as its communications architecture. Traditional bus architectures can't meet the requirements of parallel communications, and with the number of processors increases, communication efficiency even reduces, and becomes a bottleneck restricting the overall performance. In this paper, we design and implement the communication architecture based on AXI bus protocol in RTL-level. On the basis of research on AXI bus communication architecture, the paper did some basic exploration of high-density computing, parallelism exoloiting and how to optimize the performance of multi-core. The main job of this paper is as follows:Fisrt, this paper designs and implements multi-core systems platform based on AXI bus architecture, focuses on various sub-module design of the bus.Second, with matrix operations as an example, we study on high-density computing, explore the influence of different workload and communication architecture. Experimental results show that small and medium-scale design, multi-core system based on AXI bus architecture has excellent performance of speedup ratio.Finally, this paper chooses MPEG-4 video decoder as a practical application case to explore the implement and optimization of complex computing issue in MPSoC. If we realize a complex computing directly in MPSoC, it can not achieve desired results. According to the character of hardware and arithmetic, we must optimize the system to balance the workload and bring the advantage of parallel computing into play. |
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