YAK SOC-based Interface Soft IP Design And Verification

With the development of semiconductor technology, IC designers can be integrated more and more complex functions into a single chip. SoC is generated Under the general direction of the integrated circuit (IC) to the Integrated System (IS). From the narrow point of view, it is information systems on-chip, and is the system integration on a chip; from a broad perspective, SoC is a micro system, if the central processing unit (CPU) is the brain, then the SoC is the system that includes the brain, heart, eyes and hands. The emergence of SOC make integrated circuits into an integrated system, the electronic machine's function can be integrated into one chip. In the near future, the line between integrated circuits and electronic machine will be completely broken.SoC design entry threshold is the greatest expertise, IP libraries, and SoC bus architecture support. Require extensive IPs and multi-function integrated with the client logic to meet the needs of our customer's product development. With rapid development many third-party IP vendors, their success has a unique and valuable IP, or has a good reputation in the library. SoC designers reuse proven IP, not only the advantages of using the latest technology, but also reduce development time and risk.In this paper, according to the architecture of YAK SOC, Completed YAK SOC Interface IP soft core design and verification, provides a guarantee of flexible application of the YAK SOC, These design of three IP soft cores, including SPI, IIS, and IIC, in order to achieve chip application flexibility. To achieve normal communication between modules, this paper first analyzes the design method based on the standard bus. Bus-based design can be integrated into the YAK SOC system to the module succesefully. Moreover, this paper gives in detail of complete method of IP module. Finally completed the IP soft core testing, and shows the correct of the design of YAK SOC interface IP soft core.The result of this paper has some useful supervising meaning and application value for SoC system design.