Design And Implementation Of Speech Denoising FPGA System Based On Wavelet Y

Speech is the most convenient communication and the most effective media, but in the process of its transmission vulnerable to the noise. The noise will seriously affect the quality of speech signal, and subsequent processing of speech signal, such as endpoint detection, feature extraction, speech recognition, etc, and can cause difficulties caused by the deviation error. Even Therefore, to the speech signal with noise denoising become an indispensable step in signal processing. Wavelet denoising as in the field of digital signal processing, and its theoretical research in engineering application are still widely value.In recent years, along with the rapid development of semiconductor technology, increasing the scale integrated circuit technology research and the improvement of wavelet de-noising, speech technology will no longer confined to the traditional theory analysis and simulation algorithm design and etc, but with DSP and FPGA, ASIC etc hardware platform, combining gradually to the practical direction.This topic in the basis of previous work, studies the wavelet transform and the wavelet de-noising theory, wavelet threshold denoising in speech denoising of hardware, according to the characteristics of speech signal to deal with, through the proper selection of wavelet and Altera on FPGA design in modules, fully using the hardware circuit realized the phonetic wavelet threshold denoising system, which can be used to generate a hardware core, in order to meet different occasions for real-time adaptive speech signal de-noising demand.This system is designed based on overall development platform, DE2 respectively by using DSP Builder and Verilog HDL programming language with two kinds of hardware realization schematic diagram of the key to construct wavelet threshold denoising module, and by MATLAB tools for system design and simulation software model. These two kinds of hardware realization strengths: Altera DSP Builder operation platform in MATLAB graphical interface of Simulink, it can be on Simulink and DSP Builder and Altera intellectual property (IP) nuclear MegaCore graphics module calling and rational layout to realize complex electronic system design, the design documents through comprehensive compilation after conversion can be downloaded to the FPGA development board, so this system is using DSP Builder design process is convenient, intuitive and can greatly shorten the cycle of the design characteristics of DSP, first using it on wavelet threshold denoising module construction, in order to Verilog HDL programming language behind by combining principle diagram module implements the contrast test, Verilog HDL language programming combining realization schematic diagram of the way to optimize the system design, reduce resource consumption, and compiling faster.This paper is the core content in the following aspects:(1) on the wavelet transform and the wavelet denoising based on a review of related theory, this paper expounds the use FIR filters, sampling unit to construct wavelet filter the feasibility of design. (2) research on hardware and building can be calculated adaptive threshold value calculation module of the threshold, thus increasing the adaptability of the application system (3) through the simulation research of optimum threshold function setting method, and the construction of FIR filter mode, makes a comparative study of the optimal scheme is selected from applied to realize wavelet threshold denoising module. (4) respectively by means of two different types of hardware realization based on wavelet threshold denoising speech with FPGA system, and technology platform with MATLAB parallel to compare the results, meanwhile compared to compare the two hardware implementations of the advantages and disadvantages.