Research And Development Of State Machine Model Emulator Based On UML2.0

At present, UML has become the standard software modeling language. UML state diagram describes dynamic behavior of the system in its life cycle. With the expansion and increase of the system scale and complexity, UML state diagrams often contain designers' unanticipated risks. How to ensure the accuracy of the model becomes a new problem which software developers are facing. But the state machine model simulation technology has provided an effective solution to solve this problem, which has become a research focus.Research on problems of system model simulation and verification is presented in the paper, which has quest the methods of model emulator development based on UML2.0 as well. Flexible simulation software of UML state machine model has been designed in the paper based on UML2.0 model and cored in state machine model. At first, we introduced the basic elements of UML modeling language, state machine model and simulation technologies in this thesis. After that we focused on the structure of state machine model emulator designed in the paper. Then we analyzed and probed methods of semantics conversion between diagram and input language of emulator engine, construction method of state machine model emulator based on EMF and GEF, and state machine verification based on SMV language, which has proposed effective solutions. Next we introduced technologies of design and implementation of UML state machine model emulator, and then described methods of state transfer and interface implementation of emulator engine in details. Finally we have tested choice, fork and join, and composite state machine with emulator developed in the thesis. The result indicates that it has a well applicability and accuracy.