The Mmu Coprocessor Simulation Model And Software Simulation To Achieve

Embedded software is used widely in life and industry. Hardware simulator is an important tool to run, debug and verify embedded operating system or applications. Simulator is often mission-critical, therefore it must be highly trustworthy. Trustworthy simulator requires correct models to represent it. Memory Management Unit (MMU) coprocessor is a central part in microprocessor. It is necessary to design and implement a reliable MMU software module for a simulator.In this thesis, the hardware architecture and principle of the ARM926EJ-S microprocessor are introduced at first. And then the MMU architecture, the architecture of caches accessed by MMU, and the MMU transaction processes are highlighted. On this basis, we build models for the cache hardware, including TLB, Cache, and WriteBuffer, to describe their architectures and attributes. Next we build component-based models and FSM-based models for MMU transaction processes, which include Fault Check Process, Address Translation Process, Load Instruction Process, Read Data Process, and Write Data Process. The Fault Check Process includes Address Alignment Check, Translation Fault Check, Domain Fault Check, and Permission Fault Check. The component-based model describes the component and architecture of the MMU's transaction, and the FSM-based model elaborates the state transition and events when a transaction is dealt with.Using the component-based models and the FSM-based models, we design the algorithms and implement them for the MMU module. Then the MMU simulated is applied to hardware simulator, and the experiment case is conducted. The results of the case study demonstrate that the models built for MMU are correct and usable, and the effects are similar to what the MMU hardware accomplishes.