Stability And Frequency Compensation Technique Of Capacitor-less LDO

This paper focuses on the study of stability and frequency compensation technique of capacitor-less LDO which is suitable for the SoC appliances. On the basis of analysis for the pole-zero location and the stability of conventional LDO with off-chip capacitor and the basic LDO structure, the basic compensation method of capacitor-less LDO is described in this paper. Furthermore, DFC(Damping Factor Control) frequency compensation technique is analyzed deeply. After the analysis and design of PMOS power transistor, feedback resisters, bandgap reference, error amplifier with DFC block, bias block, over temperature protection block and over current protection block, a practical capacitor-less LDO with improved DFC circuit is achieved. Based on CSMC 0.5μm CMOS process, the improved LDO circuit is realized in this paper, which works stably with the load current range from 0 to 500mA. The input voltage range is from 2.7V to 6V, output voltage is 2.5V, and the least dropout voltage is below 196mV.Simulation results by Cadence Spectre indicate that the improved LDO circuit solves the stability problem of capacitor-less LDO, and it still works well even when the load current drops down to 0, which extends the application range of capacitor-less LDO.