Research And Implementation Of The Image Parallel Compression Based On MPSoCs

The demand for computing power and throughout continues to increase in virtually every domain, from general computing applications to multimedia services. In the past, performance increase in single-core processors was mainly reached by increasing clock frequency and designing more complex systems. In the meanwhile, Multi-Processor System-on-Chip (MPSoC) architectures have emerged as a popular solution to the ever-increasing performance requirements. MPSoC architectures execute multiple applications concurrently, while also requiring low power consumption. Such systems can be found in image/video encoding devices. Accordingly, the image parallel compression research on the multi-core architectures becomes very important in the application of the multimedia field.Based on the multiprocessor research and the joint picture compression (JPEG) algorithm, an image parallel compression algorithm is presented based on the Multi-Processor System-on-Chip (MPSoC) in this paper. The paper is organized as follows: Firstly, a broad overview of JPEG compression algorithm is given thus far in Section 2,the program partitions are created based on the different stages of processing from a standard JPEG encoding algorithm (such as the RGB to YCbCr conversion, DCT, quantization, zero run-length encoding, and Huffman encoding). Then, the compression algorithms on one, two and four threads using the OpenMP compiler are simulated separately in Section 3. Finally, in Section 4 the multi-core platform which this case study is based on is specified. Also, the homogeneous and heterogeneous configurations and experimental methodologies of the JPEG parallel algorithm used to partition and organize the multiprocessor configurations are reported. Then the performance improvements for each system are analyzed. Finally, in Section 5 the conclusions are summarized and a JPEG parallel algorithm based on the architecture of sixteen- processors is presented.