Research Of High Voltage MOS And Its Reliability In Power Integrated Circuit

Power integrated circuits integrate low voltage control circuits, protection circuits and high voltage power MOS. In this way, the performance and stability of the systems are greatly improved and the cost can be reduced at the same time. Power MOS is the core of power integrated circuits. Therefore, the research of Power MOS and its reliability issue is of great significance. The work of the paper can be divided into two parts: investigation on reliability problems of NLDMOS and optimized design of PEDMOS in PDP scan driver IC.Hot Carrier Injection (HCI) effects and degradation under avalanche breakdown (BV degradation) are two important reliability problems in power switching circuits, which are mainly discussed in this paper. Hot carrier reliability has widely attracted attention, but the degradation phenomenon and conclusion by different researchers have not reached agreements, so further research is required. Degradation induced by avalanche breakdown is a special reliability issue when NLDMOS is applied under unclamped inductive switching. Little research has been done to address the degradation mechanism. So it's worth studying to improve the reliability evaluation system.The implementation of PDP scan driver IC is Science and technology project of Zhejiang province. During the research, Breakdown voltage of HV-PEDMOS is found to be lower than HV-NVDMOS, limiting the maximum voltage of the chip. The optimized design is proposed and the test results prove to be good.The contents of the paper include:1. Hot carrier effects of UG-NLDMOS and SG-NLDMOS are investigated in detail by DC voltage stress, TCAD simulation and Charge Pumping test. Different degradation mechanisms are presented due to different device structures. The degradation of UG-NLDMOS mainly happens in the spacer region near the drain contact, which is caused by interface states generation. The degradation of SG-NLDMOS is much more complicated. When stressed under middle Vgs, interface states and positive oxide trapped charge generation in the accumulation region under the poly step cause the degradation. When stressed under high Vgs, interface states formation in the spacer region near the drain contact plays the leading role. Different optimizations should be taken due to different degradation mechanisms. It is presented that the hot carrier injection of NLDMOS is located in the drift and Ron is the most sensitive parameter. HCI in the channel is negligible, which coincides with the fact that the threshold voltage seldom changes. HCI of NLDMOS is greatly different from that of NMOS. 2. Degradation induced by off-state avalanche breakdown is investigated by current pulse stress, TCAD simulations and Charge Pumping test. Degradation behaviors of UG-NLDMOS and SG-NLDMOS are analyzed and degradation mechanisms are presented. Also, comparison has been made between hot carrier effects and degradation under avalanche breakdown condition.3. HV-PEDMOS of a PDP scan driver IC is optimized. The device structure and process parameters are modified by TCAD simulations and analysis. PCM and the chip are taped out in Silan. The breakdown voltage of HV-PEDMOS increases from 170V to 185V. The maximum voltage of the chip reaches up to 180V, compared to 170V initially.