Research And Design Of The Dual-Field ECC Co-processor Architecture

Flexibility and high speed are the two main target of cipher algorithms. Actually the elliptic curve cryptosystems have high speed because most of them were designed and optimized for special field and parameter. But if the algorithm was changed or needed these systems support other applications, the disadvantage of low expansibility was revealed. The thesis started with analyzing the basic operations of ECC and modern computer architecture. The design of ECC co-processor which support prime field, binary field, selectable ECC parameters and field polynomials was researched.This thesis analyzed the ECC algorithm deeply and researched the parallel degree in arithmetic level. A parallel arranger algorithm which can rising 30% calculate speed of dual fields scalar multiplication was presented. A parallel co-processor architecture based on VLIW was designed. The thesis analyzed basic arithmetic operators and abstracted the instruction system of co-processor. Basic instruction operations and instruction slot were presented. The thesis analyzed the constitute structure and storage characteristics of ECC, and designed the two read/write 32x32x12 bit RAM matrix to fulfill the storage requirement. The implement measure of dual field modular add/sub, modular multiplication and modular inverse were presentedThe ECC co-processor based on VLIW was designed. The co-processor which can complete dual fields, selectable ECC curve and parameters has high flexibility and expansibility. The parallel architecture has upper cipher processing performance and the ability of rise the operation speed greatly.