ASIC Design For Multi-value Segmented Image Connected Components Labeling

According to the problem of bottleneck of the real_time image analysis system, A VLSI implementing approach of connected components labeling is proposed,which is used for statistic characteristics calculating and fast contour following . Major work in this thesis is the implementation of equal-table:Major work in this dissertation is:According to a connected components labeling algorithm used for multi-value segmented image with hardware, complete the architecture design and circuit design of equal-table module.A special approach with FIFO is proposed,wich can implement parallel processing of equal-table module and labeling module.By analyse of test, 8 depths FIFO can complete parallel processing of equal-table module and labeling module and reduce the area of memory ,as well reduce the time cost. The module of equal-table consists of FIFO controller, the module of equal-table initiative processing, the module of equal-table processing and compressing, memory of eaqual-table, the interface of equal-table memory, the module of equal-table first-stage processing controller, the module of equal-table processing and compressing controller and the circuit of related data of equal-table controlling module. All modules are tested with ModelSim SE 6.0.The ASIC can achieve a total processing 1GOPS with a 50MHZ system clock. The ASIC can label 320*256 image within 6.8ms in 50MHz system clock. Output result of the ASIC can significantly reduce time cost of real-time image analysis system.