Research And Implementation Of Bit-Process Unit And Dual-MAC Unit Of FT-C55LP DSP

The research work is part of a project aimed at the design of a high performance low-power 16-bit fixed-point digital signals processor (named FT-C55LP). The target of FT-C55LP is compatible with TMS320C55x DSP. This paper focuses on the Top-Down design and Bottom-Up verification of two computation units of FT-C55LP which are Bit-Process unit and dual-MAC (dual Multiply-Accumulate) unit.Through a deep study of the architecture of FT-C55LP and all the instructions related to Bit-Process unit and dual-MAC unit, the functional and structural design of the two units are designed.Bit-Process unit consists of two sub-units which are dedicated bit-field processor and shift bit-processor. The bit-field processor is a special hardware that implements bit counting, bit-field extraction, bit-field expanding and exponent counting. By analyzing and comparing various kinds of realization, a dedicate bit-field processor is presented in this thesis, which implements all the special bit-field functions effectively by utilizing dedicated extractors, expanders and selectors etc. An improved multi-functional 40-bit barrel shifter is presented in this paper, which inherits all the advantages of traditional shifter and carries out all the shift functions of FT-C55LP, including arithmetical, logical, rotary and dual shift. Besides, by parallel shift overflow detecting and saturation, the parallelism of DSP is increased and the power dissipation is reduced extremely, and optional rounding is added to the design to ensure high computational precision.Dual-Mac unit composed of two similar MACs, each of which can perform a 17-bit×17-bit multiplication (fractional or integer) and a 40-bit addition or subtraction with optional 32/40-bit saturation in a single cycle. Based on a deep research of the key techniques of fast multiplier and various implementation of multiply-accumulator, an improved Radix 4 booth algorithm, limited sign extending technique with amended sign, and the altered Wallace tree which combines 3-2 and 4-2 compressor are used to implement the efficient dual-MAC unit, in which the special sign amending technique plays an important role on the realization of parallel overflow detection in multiplication. Besides, by optimizing the algorithm, an optional rounding is implemented. The dual-MAC unit architecture provides high performance and low power dissipation through increased parallelism and increased data processing throughput per cycle.Then a detailed test scheme which has the characteristics of making the subsystem verification integrated, functional verification completed and data verification perfect is worked out. According to the scheme, the two computational units are simulated. And the code coverage analysis is made with Modelsim.In the end, using Design Compiler and SIMC 0.13um COMS process, synthesis of the two computational units and their sub-units is worked out at a voltage of 1.2V, a temp of 25℃and a frequency of 200 MHz, the result of which meets the requirement.