Research Of Stream Architecture: Simulator And Verification Techniques

Stream architecture is a emerging computer architecture which has enormous performance for applications with great data parallelism such as scientific computation and media processing. This thesis researched the techniques of stream architecture simulator, which can be used to support the exploration of the design space of stream architecture, to assist the functional verification of the stream processor and to provide upper layer software with an emulation environment.Firstly, the architecture of processor X was presented, including the stream level architecture and the kernel level architecture. Stream level manages the transport and scheduling of data streams, while kernel level processes these streams.Secondly, the design of architecture level simulator of processor X was presented. The simulator is designed using the modular methodology, with each hardware component having a corresponding software component in the simulator. A cycle based simulation algorithm enhanced with module sorting to reduce the number of state-copy operations is adopted in the design of the simulator. A modeling technique which separates the functional interface and timing interface of hardware component is used to facilitate the seamless integration of functional simulator, timing simulator and debugger. Besides, an algorithm is designed to emulate the floating point fused multiply add operation which is present in processor X but not in x86 processors. At last, a method which can fully utilize multiple host processors is used to simulate multi chip interconnection.Then, based on the simulator of processor X, we designed the verification platform using PLI interface. The platform can support the functional verification both on module level and system level, and is especially suitable for coprocessor verification.At last, the simulator was implemented in C++ programming language. Lots of experiments showed that the simulator can accurately model both the functional and timing behaviors of processor X. By comparing the trace of simulator with that of the processor RTL model, design faults can be quickly and accurately located. The simulation results of representative arithmetic applications showed that the simulator had a lowest speed of 110K cycle/second, and a highest speed of 260K cycle/second. The verification platform which support complete stream application simulation is also implemented with C programming language and PLI.