A SATA2 Transmission Interface Video Capture System Design Based On FPGA

With the rapid development of communication technology, multimedia and computer vision technology, more and more systems requiring not only transmitting and processing those digital video data which is stored data storage devices, more importantly, but also being able to obtain real-time dynamic image information and process those information in real time. Therefore, The method of how to collecting and processing digital video data of these applications had become a new important research field.The dissertation analyzed the various existing video transmission systems. After that the dissertation conducted a comprehensive analysis of a variety of transmission speed interface requirements, implementation cost, the applicability requirements, and the dissertation issued the design based on the SATA2 a transmission interface, and used the DDR2 SDRAM as the buffer for video data. Xilinx's Virtex5 series FPGA as the core control devices achieved the high-speed real-time video capture system design.The main researches work has three aspects: the protocol analysis and realization, hardware design, simulation and testing.Firstly, the dissertation analyzed the physical layer, link layer, transport layer and application layer in SATA2 protocol and illustrated the detailed implementation of the protocol. After that the dissertation conducted the hardware design on Virtex5 series FPGA.Secondly, in order to meet the requirement of real-time system, the system need to cache video data in the operation, for which the dissertation used the DDR2 SDRAM controller design to balance the sudden flow. The dissertation analysis the protocol of DDR2 SDRAM controller conducted the implementation on Virtex5 Series FPGA.Finally, in order to verify the logic function of the design, the author conducted synthesize, implement, and simulation. The dissertation had a gate-level simulation on the SATA2 protocol controller, and a simulation on the initialization operation, read operation and write operation of DDR2 SDRAM controller to verify the whole design. The testing results showed that the logic function and timing of the design is correct, they achieved the design goals.