FPGA Implementation Of Low-voltage Power Line Carrier Communication Model Block

Low-voltage power line communication is a technology which using the existing power line distribution network as transmission media to transfer data and information. The characteristics such as no rerouting, wide coverage and convenient connections and so on make it have huge potential applications and become a hot research. In recent years, both at home and abroad have started a deep research in low-voltage power line carrier communication. This technology started early and developed more maturely at aboard, but the power network in china is more complicated than the foreign network, moreover, with complicated structure and big noise and uneven distribution of the domestic network, the application of foreign chips in domestic are unsatisfactory. Although PLC technology at home has made a great progress, the chips can only transmit data in the short distance, can not crossover transformer and often receive error data. Therefore, in this paper, I decide to design a module which is suitable for the low-voltage power line.My thesis analyzes in great details the attenuate characteristics and the impedance characteristics of the power-line channel. Then, the noise characteristics of the power line and its classification was discussed, analysis the power line channel noise frequency range of 30～500KHz.At the end of the second chapter build the channel models of the power line. In the third chapter I adopted spread-spectrum modulation scheme for the low power line's special working environment, then introduce the principle of spread spectrum technology and analysis its characteristics, especially emphasis the direct spread spectrum communication system, introduce its working principle and its key technology.When adopting programming with hardware description language (HDL) to design digital circuit, the designer can modify and update the design flexibly which shortened the design time, so I adopt FPGA to achieve the module design. In order to facilitate the realization of the module, I divide the design into several sub-module by function and finish them one by one, eventually integrate them into a modular system. In the paper I mainly introduce the PN code generation module, RS coding, FIR filter, CIC filter, DDS signal generator, bit synchronization and Rake receiving module design, each module programmed with Verilog HDL, meanwhile I also use MATLAB software as auxiliary tool to generate the FIR coefficients and the lookup table of DDS signal generator.In the end of the paper, all the sub-module was instanced into a top-level system module, then I selected the suitable FPGA chip to download the design.Eventually built the hardware test platform to commplete the entire module performance test, and the results indicate that my design can realize the required functions.