IP Core Research And Design Of Image Digital Watermarking Algorithm Based On Lifting Wavelet Transform

Digital watermarking is one of the technologies of hidden information. It is an active application of hidden information. Digital watermarking has played a very important role and been widely used in copyright protection and authentication of works of art such as audio-video products. However, most of the digital watermarking research and application are based on software implementation, whose speed is slow and can not meet the requirements of real-time processing. Therefore, the use of hardware to implement digital watermarking has important practical value and significance.This paper adopts the semi-custom ASIC method to design the enhance type of wavelet transform module, digital watermarking algorithm and embedding modules, use top-down code description of Verilog HDL as design input methods to create various parts IP soft-core of Digital Watermarking, and ASIC design method is used to generated IP solid-core on this basis.In this paper, the main works are the following aspects:1) The algorithm and hardware architecture of the enhanced type of wavelet transformation in digital watermarking are studied. The enhanced type of wavelet transformation is one of the key algorithms to the implementation of digital watermarking. This paper analyzes the enhanced type of wavelet transformation based on the wavelet transformation and discrete wavelet transformation which have been raised by elder generation. How to deal with the borderline and assembly line at the beginning and ending of the enhanced type of wavelet transformation are also studied in this paper. Verilog language is used to describe and simulate.2) This paper deals with the digital watermark embedding sequence generation and IP-core design and simulation. This paper divides the pictures into several bit-plane and uses m sequence (pseudo-random sequence) to embed meaningless watermarks at the lowest bit-plane.3) This paper has designed and analyzed cover model of ASIC to these modules and got the IP hard-core. This part use EDA design tools to work, which mainly have the Design Compiler (Synopsys logic synthesis Tools Company), Silicon Ensemble (Cadence's automatic placement and routing tools).