Design And Implementation Of A 5GHz LC_Tank PLL For 802.11a

The wireless network technology has consumedly extended the area of network. With the rapid development of technologies, various high speed or super high speed wireless networks have been promulgated. There are kinds of wireless data communication standards; Just for IEEE, there are four standards used in wireless data communication standards: IEEE802.11, IEEE802.11b, IEEE802.11a and IEEE802.11g. Furthermore, Blue tooth and HomeRF have been used in the wireless network. IEEE802.11a works in 5GHz frequency band, which keeps away from 2.4GHz band, which has been adopted by microwave, Bluetooth and mass of industry equipments. Because of the less anti-jamming and data communication band of 54Mbps, IEEE802.11a becomes the preferential standard in the wireless network.In super speed wireless communication, PLL (Phase Locked Loop) is a basic part, which is used by frequency transfer to produce an accurate local clock signal. Under earlier CMOS technology, only a few passive elements, such as resistor and capacitor, could be used, which restricted the improvement of operating frequency in PLL in great measure. With the rapid progress of CMOS technology, on-chip passive inductor has been implemented. With the use of passive inductor, the realization of super speed is possible.In this paper, a 5GHz super high speed PLL is designed based on on-chip passive inductor and adjustable capacitor in 0.18μm CMOS Process. The main content includes: A model for passive inductor is set up in ASITIC to analyse quality factor characteristic deeply; A new structure of linear adjustable capacitor is introduced, based on thorough analysis of multiple models of variety of adjustable capacitors in ADS. Comparing simulated results of different kinds of negative oscillators in ADS, a NMOS-PMOS cross coupling negative oscillator is finally adopted; By means of principles of frequency-mixer, a kind of injection locking frequency-divider is designed to overcome the difficulty that ordinary frequency-divider is hard for frequency division in high operating frequency; And a locking-dection circuit is presented on basis of delay property of smit trigger.The simulation results show that PLL in this paper has advantages of high precise, low jitter, and low power-consumption, and could be locked in terms of TT,FF and SS. The simulated RMS and peak-to-peak jitter of 5GHz output clock are 241.04fs and 1.0909p, respectively. The whole chip has power-consumption of 26mW and area of 0.67mm2, satisfying requirements of IEEE802.11a.