Development Of An Automated Flow For Fault Simulation

As technology advances, in one hand, microcontroller becomes smaller and smaller, in the other hand, manufacturing difficulties becomes bigger and bigger which, as a consequence, lead to design and test complexity dramatically enhanced. Therefore, sort good and bad chip becomes a really tough work. To test a design with functional test vectors and to measure the quality of test vectors with fault simulation becomes more and more important even mandatory. This thesis proposes the development of an automatic way to perform fault simulation which is used to measure the quality of the functional test vectors.