RF Characteristics Of CPW Based On SOI Substrate

As operation frequency and integration improved,RF circuits on low resistivity Si substrate perform poorer because of high energy loss and serious crosstalk through the substrate.With its smart structure,SOI offers many advantages over bulk Si CMOS technology such aslow crosstalk,low parasitic capacitance and many other excellent electromagnetic properties in high frequency.In order to obtain good performance of RF SOC,it is important that passive components with low loss and low parasitic effect are made.In recent years,passive devices on SOI substrate have got considerable amount of research and gained some development.Coplanar waveguides(CPW) are widely used as interconnects and matching network in MMICs.It is important to design low loss CPW to obtain high performance MMICs.In this paper,two kinds of 50ΩCPWs are designed on SOI substrate by HFSS. For comparison,same CPWs on high resistity Si are fabricated.The tested result shows that CPWs on SOI could get fine transmission characteristics.CPWs fabricated on SOI substrates with four groups of substrate parameters perform differently.The parameter influence of SOI substrates are obtained as follows.Increase of substrate resistivity and buried oxide thickness make better performance.The influence of surface Si thickness depends on resisitivity of surface Si.Based on the fine performance of a 50ΩCPW fabricated on SOI substrates,a dual-termination coupled Ka band bandpass filter(BPF) and a bandstop filter(BSF) have been designed and fabricated.The best BPF on SOl shows -4.23dB insertion loss at peak transmission of about 32GHz.The best BSF on SOI shows -15.3dB insertion loss at peak transmission of about 25GHz.They gain close characteristics respectively to the same structure on high resistivity(p≥1000Ω·cm) silicon substrate.In order to get well-behaved CPW,a novel low-loss 50Ωcoplanar waveguide with MEMS structure on SOI substrate is proposed.Through a CMOS-compatible process and anisotropic etch of silicon,surface silicon of SOI between the signal line and grounds is removed.The measured result shows that the proposed MEMS CPW owes about 50%less loss than the conventional one in high frequency up to 40GHz. The phenomena that the insertion loss is between that of conventional and MEMS CPWs are explained by study the model of CPWs on high resistivity Si substrates with different oxide strctures.