Research Of Fast Computation Technology In Wireless Sensor Networks Node

As a novel technology about acquiring and processing information,Wireless Sensor Network is widely used in military,industrial controlling,environmental monitoring and medical assistance fields.The WSN nodes are featured as low in power and cost,and convienent to place.In such applications that WSN involved,the most important is how to localize a target and process real-time data fast.So applying an efficient,fast and easy-to-realise computation method into WSNs node lacation is really a popular topic.In the modern fast computation methods,DSP is hard to realize high speed and complicated algorithms.Along with the development of PLD device and EDA technology,the advantage of the signal processors based on FPGAs in the performance,cost,flexibility and power consumption standed out,but it is awfully complex to realize some algorithms by pure hardware language.In the embedded SOPC system,we can effectively use the advanced language,such as C++,to control data,and use the hardware language to realize algorithm.It can resolve the above problem and fulfill the signal processing tasks in real-time with the high speed.In this thesis IIR filter based on FPGA is designed and cross correlation algorithm is realized.Firstly,the architecture of WSN and research necessity of fast computation are introduced,Secondly,several digital signal processor such as MCU,DSP and FPGA are compared,and their advantages and disadvantages are analyzed.FPGA Based on SOPC is proposed.The adder and multiplier are discussed in terms of resource utilization and speed. Based on this,IIR filter and cross correlation algorithms which was usually used in node localization are analyzed.Then according to researching the character of FPGA,the clock and data are programed by C++ with NiosⅡ.The main algorithm is programmed by hard description language.In the end,according to looking into data output,the result of algorithm and performance of FPGA are analyzed.The results proved that the function of design is correct.The speed of algorithm is improved greatly and hard resource is economized.The design indicates the feasibility of this method.