The Design Of 2.7W Double Channels Stereo Class-D Audio Amplifier

With the request of energy-saving and microminiature electronical production, power amplifiers that possess of low distortion and high efficiency have been studying currently. In despite of low distortion in traditional linear amplifiers, the efficiency is not high, furthermore, it must fix large radiator.with the characteristic of high integrated, low dissipation and small area, The Class-D audio power amplifier, which adopts CMOS process, has the widely application in portable electronic devices such as PDA, mobile phone, MP3 player.In this paper, we first introduce the audio amplifier development, principle, category and some particular parameter. And then analyse the Class D system, include of modeling the feedback loop, the architecture of H-bridge drive, the design of filter, and the caculation of efficiency. Then make a thorough presentation and analysis of the circuit .whereafter, introduce the layout optimazation detailly,the ESD design, and the principal of snapback. At last, announce the test results of MPW.The designed Class D can work proper under supply voltage of 2.5V to 5.5V, and the maximum output power per channel is 2.7W. It has the advantage of little of ancillary equipment and without filter, that can save the space of PCB. The main circuit is contact of input stage amplifier, triangular wave generator, PWM module, Power drive modulator, power output stage, over temperature protect circuit and over current protect circuit. The output power, THD and dead time is especially taken into account in this design. On the side of layout, we adopt common centroidal principal axis match to reduce the offset the differential amplifier;separate the sensitive signal from digital module with ground wire;Insulate the right and the left sound track for reduce cross-talk. After chip measurement ,the efficiency of which is 90%, the quiescent current is less than 5mA, the shutdown current is 0.1μA, PSRR is greater than 75dB, and THD is less than 0.15%, reach the project indicators. The chip has been producted with 0.35μm N well CMOS proccess in Semiconductor Manufacturing International Corporation ( SMIC).