| A 2.5W filterless class D audio power amplifier chip is discussed and designed in this paper. Firstly, basic theory and the system topology of the audio power amplifier were given in detail. Then the factors affecting the performance, such as PSRR, THD and efficiency, were analyzed. According to the design specification, a low power single loop NPWM class D amplifier was implemented in this paper. The main sub-circuits were designed, including the voltage reference circuit, pre-amplifier, auto power compress (APC), the gate driving control circuit, linear triangular wave generator.The whole class D amplifier was simulated with Cadence under single poly 4 metals (1P4M) standard mixed signal fabrication technology. This simulating result shows a good performance of the power amplifier chip , which the output power is 2.5W (THD=10%, 4?@VCC=5V), the efficiency is 87.5% ,the PSRR is -105dB in the low frequency, the offset voltage is less than 38uV and the quiescent current is less than 3.6mA. Based on these results, the layout of this chip was drawn.Lots of optimizing techniques are taken when the amplifier chip was designed, such as the negative feedback, the auto power compress (APC), controlling the slope of gate driving voltage, attenuating the"click and pop"noise, and the advanced PWM technique. The investigation shows that a high linearity, low EMI class D amplifier can be achieved, and this design can achieve a filterless output of class D audio power amplifier. The chip should decrease the system area and cost to improve the marking competition. |
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