The Optimization Of AVS Video Encoder Architecture On Davinci DSP

Video compression is a key technology of multimedia system, and is also the pivotal software modules in multimedia application. At present there are three primary methods to realize the video encoding algorithms, including encoding by software running on PC, system based on ASIC and embedded system based on DSP. However, because of the excellent calculating ability and flexibility, DSP systems become the dominating scheme to implement the video encoding algorithms gradually.Davinci DSP, the latest products which are manufactured by Texas Instruments is a perfect resolution to the multimedia application. Davinci DSPs are based on dual-core architecture and combined with a general processor core, ARM926E, and a C64X+ DSP core. Besides, it uses Codec Engine and VISA (Video, Image, Speech, Audio)interface to realize the communication between the two kernels,which facilitates the development of algorithms. Undoubtedly, Davinci DSPs will have very broad perspective in the multimedia application domain in the following years.AVS is a video and audio coding standard brought forward by China. As the other multimedia algorithms, it still processes the data stream and need great bandwidth and calculating ability, and only the system with high performance can match the requirements. According to some relative dissertations, cache performance plays a significant role in the DSP system running video coding algorithms. However, the classical video coding algorithms use macroblock as the basic processing unit and all the macroblocks in a frame should be done sequentially, and such a scheme make the cache performance very low. For the sake of solving this problem, respective analysis to the instruction cache and data cache performance is given in this thesis, which also brings forward the optimization of the video encoder running on Davinci DSP. On behalf of the instruction cache, the stage-encoding scheme is put forward on the base of the traditional architecture, which seperates the classical architecture into several independent stages. Such a method makes the best use of temporal locality and special locality of the instruction cache, and then improves its performance. On the other hand, data cache performance is much more decisive to the whole system than that of instruction cache. In this thesis, optimization of the data cache is given according to the data access particularity and memory atchitecture of Davinci DSP. The data placement and parameter separation are rearranged based on the optimization scheme. Besides, because of the substantive data that should be transferred during the coding process, pipeline based on DMA transfer and Ping-Pong Buffer is set up in each stage, and it improves the performance of the system greatly.